Circuit Partitioning for Dynamically Recon gurable FPGAs
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چکیده
Dynamically recon gurable FPGAs have the potential to dramatically improve logic density by time-sharing a physical FPGA device. This paper presents a networkow based partitioning algorithm for dynamically recon gurable FPGAs based on the architecture in [2]. Experiments show that our approach outperforms the enhanced force-directed scheduling method in [2] in terms of communication cost.
منابع مشابه
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تاریخ انتشار 1999